United States

In this work, we analyze interconnects with TaS2 barrier/liner by (a) building a 3D modeling framework for the line metals and vias, (b)integrating the model with the comprehensive circuit simulation flow based on synthesis and place-and-route and (c) evaluating the resistance of different levels of metals (M1-M9) and vias (V1-V8) and the circuit implications of TaS2-augmented interconnects in comparison with the conventional interconnects.

DRC 2021

Modeling and Circuit Analysis of Interconnects with TaS2 Barrier/Liner

aes circuit

interconnects

2d material

3d modeling

Brought to you by **National Defense Industrial Association ([NDIA](https://www.google.com/url?q=https%3A%2F%2Fwww.ndia-sd.org%2F&sa=D&sntz=1&usg=AFQjCNHj_BQx1K4KVKKp1NTIsAltZOG9Vg))** and hosted by the **Battlespace Exploitation of Mixed Reality ([BEMR](https://cdn.dvidshub.net/media/video/2101/DOD_108139354/DOD_108139354-1024x576-1769k.mp4)) Lab**, at **Naval Information Warfare Center Pacific ([NIWC PAC](https://www.google.com/url?q=https%3A%2F%2Fwww.public.navy.mil%2Fnavwar%2FNIWC-Pacific%2FPages%2Fdefault.aspx&sa=D&sntz=1&usg=AFQjCNFNS160IEsocfaBrnCNB3u7NqLHPw))**, and welcoming academia, government/DOD, and industry leaders who support Industrial Augmented Reality/Virtual Reality by using the following technologies:   


* Augmented Reality (AR) / Virtual Reality (VR)

* 2D/3D displays

* mobile displays

* wearables

* any other "immersive" technology

### In all fields that touch:

* 3D modeling

* Manufacturing 

* Installations 

* Maintenance and Repairs

* Construction

* Logistics

* Additive manufacturing

* Training

The technical exchange is a two day event held online this year due to COVID-19. It will feature two days of oral presentations, demonstrations, and posters from leaders in AR/VR and other display technologies, including government briefings on active projects within the DOD. The technical exchange is unclassified and we welcome participation from the Navy, DoD as well as from industry and academia. 

The goals of TEAR 3M are:

*  To spread awareness of current immersive technology research relevant to Navy/DOD applications

*  To connect AR researchers with experts in DOD to learn about needs and requirements

*  To build and strengthen collaborations within the DOD research community

![](https://assets.underline.io/uploads/markdown_image/1/image/0c13ac0ffa096b2353573964d8b89789.png)

TEAR 3M General Chairs:

Heidi Buck,  Director @ BEMR Lab, Naval Information Warfare Center, Pacific

Lauren Burnette, BEMR Lab, Naval Information Warfare Center, Pacific


For more information, contact Lauren and Heidi at:  tear3m@spawar.navy.mil

Questions regarding sponsorship/registration contact:  ndiasd@sandiegositepros.com

Conference host POC is Tammy Sanchez (NDIA):  tamsanch@cisco.com

TEAR 3M 2021

poster


**[DOWNLOAD THE DRC 2021 DIGEST](https://drive.google.com/file/d/17_-pkYf4IBbVuNYgohTf0iZJORVGp_uN/view?usp=sharing)**

**[DOWNLOAD A COPY OF THE FINAL DRC PROGRAM](https://drive.google.com/file/d/1Ek8UIDCowpLq0z2hXav5tn67FboxS03N/view?usp=sharing)**

For almost eight decades, the Device Research Conference (DRC) has brought together leading scientists, researchers and students to share their latest discoveries in device science, technology and modeling. Notably, many of the first public disclosures of key device technologies were made at the DRC. This year marks the 79th anniversary of the DRC—the longest running device research meeting in the world. As we commemorate this meeting, the high-caliber technical sessions will be highlighted by plenary talks and invited talks by international research pioneers and leaders behind modern electronic technology.

Given the ongoing global health concerns associated with COVID-19 (Coronavirus), the DRC leadership has decided to hold the 2021 Device Research Conference in a virtual (online) format. This follows an enormously successful 2020 DRC held virtually, in which we had record attendance and worldwide participation of more than 875 attendees from 33 countries.

The 2021 Conference will feature:

* Informative, timely short courses in rapidly developing fields
* Oral and poster presentations on electronic/photonic device experiments and simulations
* Plenary and invited presentations given by worldwide leaders
* Evening “rump” session
* Strong student participation and Student Paper Awards

DRC is held in coordination with the Electronic Materials Conference (EMC), which will occur the same week, from June 23-25. As has happened in person in past years, in 2021, the virtual DRC and EMC sessions on the shared day, Wednesday, June 23, will be open to all attendees from both conferences. This recognizes the strong interaction between device and electronic materials research and provides fruitful exchanges of information between attendees of both Conferences. For information on the 63rd Electronic Materials Conference, please visit the [EMC 2021 website.](https://www.mrs.org/63rd-emc/)

2021 DRC individual presentation videos will become available in Underline at the end of each technical session. A recording of each full live session with Q&A will be posted later during the conference. To facilitate re-viewing of recorded talks and sessions, the DRC Underline site will remain open through 11:59pm (US EDT) on July 7th. DRC Conference registration will remain open at www.mrs.org/drc-2021/registration through June 30th.

Thank you for joining us at the 2021 Device Research Conference!

**General Chair**
<br>Zhihong Chen, Purdue University

**Technical Program Chair**
<br>Becky (R.L.) Peterson, University of Michigan

**Technical Program Vice-Chair**
<br>Gregg Jessen, BAE Systems

You can register for the 79th Device Research Conference with the following link. https://www.mrs.org/drc-2021

For almost eight decades, the Device Research Conference (DRC) has brought together leading scientists, researchers and students to share their latest discoveries in device science, technology and modeling. Notably, many of the first public disclosures of key device technologies were made at the DRC. This year marks the 79th anniversary of the DRC—the longest running device research meeting in the world. As we commemorate this meeting, the high-caliber technical sessions will be highlighted by plenary talks and invited talks by international research pioneers and leaders behind modern electronic technology.

Recently, low-power analog switches have been enjoying rapidly growing interest owing to their proliferation in mobile and reconfigurable communication and connectivity systems often with multiple-input-multiple-output architecture. To develop this ideal switch, non-volatile switches based on memory devices have been investigated with the potential of zero static power dissipation. Here, we report the first single-pole-double-throw (SPDT) non-volatile RF switches based on monolayer MoS2.

Single-Pole-Double-Throw RF switches based on monolayer MoS2

We utilize analog and non-volatile resistive memory devices to construct in-memory computing platforms offering lower power and increased speed. Integration of oxide-based devices with CMOS has been performed in back-end processing, showing analog tunability of the memory elements. We demonstrate acceleration of deep learning neural networks, optimization, finite automata models and tree-based machine learning. We show the potential for significant improvement over CPUs, GPUs, and custom ASICs using these in-memory and analog systems.

In-memory computing with non-volatile analog memories for machine learning applications

Device scaling has been a critical topic of nonvolatile memory for high integration density, low operation voltage and high device speed. However, HfO2-based metal-ferroelectric-semiconductor field-effect-transistor (MFSFET) has an issue of gate leakage current when the ferroelectric HfO2 film thickness is reduced less than 10 nm. 
In this research, we realized the MFSFET with 5 nm thick ferroelectric nondoped HfO2 gate insulator for the first time by decreasing the sputtering power of Pt gate electrode deposition.


MFSFET with 5 nm Thick Ferroelectric Undoped HfO2 Gate Insulator

Heterogeneous Integration, Advanced Packaging, Dielets and Chiplets - why the hype?

Integration of Polycrystalline diamond on top of GaN and Ga2O3 devices for thermal management

The objective of this work is to develop lateral 4H-SiC power devices that could be integrated into a monolithic high voltage power IC (HVIC) chip using thin RESURF layer. Junction isolation structure between neighboring devices can be easily achieved through mesa etch. This paper proposes a high breakdown voltage lateral RESURF MESFET structure and edge termination technique using epitaxially grown thin RESURF wafer.

Design and fabrication of low pinch-off voltage 700V lateral 4H-SiC MESFET with thin RESURF layer

In this work, we present the first vertical GaN finFETs designed for RF performance. A record fmax for vertical GaN transistors is reported, and our results show a promising future for vertical GaN devices in both RF and power electronics.

Small-Signal, High Frequency Performance of Vertial GaN FinFETs with fmax=5.9 GHz

Field-Emission Enhanced Contacts for Disordered Semiconductor based Thin-Film Transistors

For the first time, we have developed CuAg/Al2O3/CuAg selector by magnetron sputtering and ALD processes, which possesses bidirectional threshold switching, steep switching slope and high selectivity (~100000). The superior selectivity and stability of the CuAg/Al2O3/CuAg selector compared to pure Ag or pure Cu as symmetrical electrodes corroborates the interface optimization of the alloying electrodes. This device provides new opportunities for neuromorphic computing and 3D stacking of RRAMs.

Modeling and Circuit Analysis of Interconnects with TaS2 Barrier/Liner

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Single-Pole-Double-Throw RF switches based on monolayer MoS2

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