France



Introduction:&lt;b&gt; &lt;/b&gt;Double CoFeB/MgO interface perpendicular MTJ has become the de facto standard technology of current STT-MRAM. However, there are still issues for high density memory application and high reliable application including Automobile applications. Furthermore, achievement of high speed and high endurance features, in the other words, high speed SRAM replacement is still challenging for STT-MRAM, because of its tradeoff relationship among the retention, endurance, and operational speed. Recently, Spin Orbit Torque (SOT) devices have been intensively researched and developed because SOT devices have the potential to achieve high speed and high endurance. To realize the practical use of SOT-MRAM for LSI applications, these issues must be addressed.&lt;br/&gt;&lt;br/&gt;This invited paper reviews our recent progresses in STT-MTAM, SOT-MRAM and Nonvolatile AI processors with CMOS/MTJ hybrid technology. The STT-MRAM and SOT-MRAM as NV working memory and AI processors as these applications are particularly suitable for future IoT / AI systems that require ultra-low-power and high-performance computing at the same time.&lt;br/&gt;&lt;br/&gt;128Mb STT-MRAM and Quad interface MTJ technology: We developed novel damage control integration process technologies including new low-damage MgO deposition process, low-damage RIE process, and low temperature SiN-cap process. By applying the developed damage control integration process technologies to double interface p-MTJ fabrication, TMR ratio, thermal stability factor, and switching efficiency of Double p-MTJ were successfully improved. Moreover, it was shown that despite the significant increase in thermal stability factor, the endurance of the fabricated Double p MTJs was over 1010. Finally, with our double-interface p-MTJ technology and novel damage control integration process technologies, fabricated 128Mb STT-MRAMs successfully achieved 14ns/7ns write speed at Vdd of 1.2V/1.8V, respectively.&lt;br/&gt;&lt;br/&gt;Next, for further scaling of STT-MRAM, we proposed novel Quad-interface p-MTJ technology which brings forth an increase of thermal stability factor compared with conventional Double-interface p-MTJ technology. We successfully fabricated the quad-interface MTJ using 300mm process based on the damage control integration process. The fabricated Quad p-MTJs achieved an enhancement of switching efficiency in addition to an approximately two times larger thermal stability factor without degradation of TMR ratio. The developed Quad p-MTJ technology will become an essential technology for the scaling of the STT-MRAM beyond 20nm without changing material and process sets from mass-production STT-MRAM. Moreover, the high reliable Quad p-MTJ technology with enough thermal stability factor is suitable for Automobile applications that require high temperature operation such as 150&lt;sup&gt;○&lt;/sup&gt;C.&lt;br/&gt;&lt;br/&gt;Field-free canted SOT-Device with 350ps write speed and its SOT-MRAM: To realize practical use of SOT-MRAM for LSI applications, we demonstrated 55 nm-CMOS/SOT-device hybrid MRAM cell with magnetic field free writing for the first time. For field free writing, we developed canted SOT device under 300 mm BEOL process with 400°C thermal tolerance. In addition, we developed its advanced process as follows; PVD process of SOT channel layer for high spin Hall angle under 400°C thermal tolerance, low damage RIE technology for high TMR/thermal stability factor, and ultra-smooth surface metal via process under SOT device to reduce contact resistance. By using the developed technologies, our canted SOT devices achieved fast write speed of 0.35 ns without magnetic field, an enough thermal stability factor of 70 for non-volatile memory (over 10 years retention), and a high TMR ratio of 167%, simultaneously. Moreover, we fabricated a field free canted SOT-MRAM cell with 55 nm CMOS technology and demonstrated its write/read performance. These technologies will open to high speed write non-volatile memory such as 1 level cache application of many kinds of application processors.&lt;br/&gt;&lt;br/&gt;CMOS/MTJ hybrid AI Processor for low power application:&lt;b&gt; &lt;/b&gt;Focusing on the indispensable nearest neighbor search (NNS) function of the brain, we developed a nonvolatile object recognition processor with NSS full-adaptive to any data format, employing nonvolatile memories base on our p-MTJ. The developed object recognition processor was fabricated under 90nm-CMOS/70nm-MTJ hybrid process on 300mm-wafer. The 4-Transistors &amp; 2-MTJs type memory cells were adopted to completely eliminate standby power. Moreover, we successfully developed a self-directed power-gating technique leveraging the non-volatility, high access speed and unlimited endurance features of the p-MTJs. This developed self directed power-gating technique was employed to shut down idle circuit blocks during not only the standby periods but also the full operation periods. The measured peak operation power consumption of the prototype chip was only 130μW and can be further optimized corresponding to the format of reference data. Compared to the latest conventional researches, the significant improvements of both power performance (about 2-3 order reduction) and circuit density (about 2 order improvement) were achieved.

**References:**

[1] S. Ikeda et al., Nat. Mater. 9, 721 (2010).&lt;br/&gt;[2] T. Endoh et al., 2011 International Electron Device Meeting (IEDM), 2011. 34&lt;br/&gt;[3] H. Sato et al., Appl. Phys. Lett. 101, 022414 (2014).&lt;br/&gt;[4] T. Saito et al., IEEE T-Magn. 54, 3400505 (2018).&lt;br/&gt;[5] H. Sato et al., IEDM 2018, p. 608.&lt;br/&gt;[6] K. Lee et al., IEDM 2018, p. 604.&lt;br/&gt;[7] Y. J. Song et al., IEDM 2018, p. 416.&lt;br/&gt;[8] C. Park et al., VLSI 2018, p. 185.&lt;br/&gt;[9] O. Golonzka et al., IEDM 2018, p. 412. 6&lt;br/&gt;[10] C. Park et al., VLSI 2018, p. 185.&lt;br/&gt;[11] T. Endoh, IEEE ISCASS2018. (Invited)&lt;br/&gt;[12] K. Nishioka et al., VLSI 2019, T11-4; IEEE T-ED 67, 995 (2020).&lt;br/&gt;[13] S. Fukami et al., VLSI 2016, T61. 10&lt;br/&gt;[14] H. Honjo et al, IEDM 2019, 28.5.1.&lt;br/&gt;[15] T. Endoh, MRAM Development Day 2019 (Invited)&lt;br/&gt;[16] T. Endoh, 2020 International Solid-State Circuits Conference (ISSCC) (Invited)&lt;br/&gt;[17] T. Endoh et al, VLSI Symp. 2020 (Invited)&lt;br/&gt;[18] T. Endoh, Tutorial of IEDM2020 (Invited)

**Images:**

![](https://assets.underline.io/uploads/markdown_image/1/image/4ab86aad73439f39476f104f23a8eb59.jpg)
Fig. 1: (a) developed 128Mb STT-MRAM. (b) photograph of its subarray. (c) Shmoo plot of subarray in 128Mb STT-MRAM. (d) Switching efficiency as a function of CD for the Quad- and Double-interface MTJs.

![](https://assets.underline.io/uploads/markdown_image/1/image/b8abc4d21c732c328f6998e190bbd9cb.jpg)
Fig. 2: (a) Developed AI object recognition processor with 90nm-CMOS/70nm-MTJ. (b) Further performance comparisons of the operation power efficiency and circuit density.

INTERMAG 2021

 Advanced MTJ and SOT Technology for AI and Automobile applications INVITED

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Introduction: Double CoFeB/MgO interface perpendicular MTJ has become the de facto standard technology of current STT-MRAM. However, there are still issues for high density memory application and high reliable application including Automobile applications. Furthermore, achievement of high speed and high endurance features, in the other words, high speed SRAM replacement is still challenging for STT-MRAM, because of its tradeoff relationship among the retention, endurance, and operational speed. Recently, Spin Orbit Torque (SOT) devices have been intensively researched and developed because SOT devices have the potential to achieve high speed and high endurance. To realize the practical use of SOT-MRAM for LSI applications, these issues must be addressed. This invited paper reviews our recent progresses in STT-MTAM, SOT-MRAM and Nonvolatile AI processors with CMOS/MTJ hybrid technology. The STT-MRAM and SOT-MRAM as NV working memory and AI processors as these applications are particularly suitable for future IoT / AI systems that require ultra-low-power and high-performance computing at the same time. 128Mb STT-MRAM and Quad interface MTJ technology: We developed novel damage control integration process technologies including new low-damage MgO deposition process, low-damage RIE process, and low temperature SiN-cap process. By applying the developed damage control integration process technologies to double interface p-MTJ fabrication, TMR ratio, thermal stability factor, and switching efficiency of Double p-MTJ were successfully improved. Moreover, it was shown that despite the significant increase in thermal stability factor, the endurance of the fabricated Double p MTJs was over 1010. Finally, with our double-interface p-MTJ technology and novel damage control integration process technologies, fabricated 128Mb STT-MRAMs successfully achieved 14ns/7ns write speed at Vdd of 1.2V/1.8V, respectively. Next, for further scaling of STT-MRAM, we proposed novel Quad-interface p-MTJ technology which brings forth an increase of thermal stability factor compared with conventional Double-interface p-MTJ technology. We successfully fabricated the quad-interface MTJ using 300mm process based on the damage control integration process. The fabricated Quad p-MTJs achieved an enhancement of switching efficiency in addition to an approximately two times larger thermal stability factor without degradation of TMR ratio. The developed Quad p-MTJ technology will become an essential technology for the scaling of the STT-MRAM beyond 20nm without changing material and process sets from mass-production STT-MRAM. Moreover, the high reliable Quad p-MTJ technology with enough thermal stability factor is suitable for Automobile applications that require high temperature operation such as 150○C. Field-free canted SOT-Device with 350ps write speed and its SOT-MRAM: To realize practical use of SOT-MRAM for LSI applications, we demonstrated 55 nm-CMOS/SOT-device hybrid MRAM cell with magnetic field free writing for the first time. For field free writing, we developed canted SOT device under 300 mm BEOL process with 400°C thermal tolerance. In addition, we developed its advanced process as follows; PVD process of SOT channel layer for high spin Hall angle under 400°C thermal tolerance, low damage RIE technology for high TMR/thermal stability factor, and ultra-smooth surface metal via process under SOT device to reduce contact resistance. By using the developed technologies, our canted SOT devices achieved fast write speed of 0.35 ns without magnetic field, an enough thermal stability factor of 70 for non-volatile memory (over 10 years retention), and a high TMR ratio of 167%, simultaneously. Moreover, we fabricated a field free canted SOT-MRAM cell with 55 nm CMOS technology and demonstrated its write/read performance. These technologies will open to high speed write non-volatile memory such as 1 level cache application of many kinds of application processors. CMOS/MTJ hybrid AI Processor for low power application: Focusing on the indispensable nearest neighbor search (NNS) function of the brain, we developed a nonvolatile object recognition processor with NSS full-adaptive to any data format, employing nonvolatile memories base on our p-MTJ. The developed object recognition processor was fabricated under 90nm-CMOS/70nm-MTJ hybrid process on 300mm-wafer. The 4-Transistors & 2-MTJs type memory cells were adopted to completely eliminate standby power. Moreover, we successfully developed a self-directed power-gating technique leveraging the non-volatility, high access speed and unlimited endurance features of the p-MTJs. This developed self directed power-gating technique was employed to shut down idle circuit blocks during not only the standby periods but also the full operation periods. The measured peak operation power consumption of the prototype chip was only 130μW and can be further optimized corresponding to the format of reference data. Compared to the latest conventional researches, the significant improvements of both power performance (about 2-3 order reduction) and circuit density (about 2 order improvement) were achieved.

**References:**

[1] S. Ikeda et al., Nat. Mater. 9, 721 (2010). [2] T. Endoh et al., 2011 International Electron Device Meeting (IEDM), 2011. 34 [3] H. Sato et al., Appl. Phys. Lett. 101, 022414 (2014). [4] T. Saito et al., IEEE T-Magn. 54, 3400505 (2018). [5] H. Sato et al., IEDM 2018, p. 608. [6] K. Lee et al., IEDM 2018, p. 604. [7] Y. J. Song et al., IEDM 2018, p. 416. [8] C. Park et al., VLSI 2018, p. 185. [9] O. Golonzka et al., IEDM 2018, p. 412. 6 [10] C. Park et al., VLSI 2018, p. 185. [11] T. Endoh, IEEE ISCASS2018. (Invited) [12] K. Nishioka et al., VLSI 2019, T11-4; IEEE T-ED 67, 995 (2020). [13] S. Fukami et al., VLSI 2016, T61. 10 [14] H. Honjo et al, IEDM 2019, 28.5.1. [15] T. Endoh, MRAM Development Day 2019 (Invited) [16] T. Endoh, 2020 International Solid-State Circuits Conference (ISSCC) (Invited) [17] T. Endoh et al, VLSI Symp. 2020 (Invited) [18] T. Endoh, Tutorial of IEDM2020 (Invited)

**Images:**

![](https://assets.underline.io/uploads/markdown_image/1/image/4ab86aad73439f39476f104f23a8eb59.jpg)
Fig. 1: (a) developed 128Mb STT-MRAM. (b) photograph of its subarray. (c) Shmoo plot of subarray in 128Mb STT-MRAM. (d) Switching efficiency as a function of CD for the Quad- and Double-interface MTJs.

![](https://assets.underline.io/uploads/markdown_image/1/image/b8abc4d21c732c328f6998e190bbd9cb.jpg)
Fig. 2: (a) Developed AI object recognition processor with 90nm-CMOS/70nm-MTJ. (b) Further performance comparisons of the operation power efficiency and circuit density.

technical paper

The semiconductor industry is actively developing high-density, non-volatile random access memories based on perpendicular magnetic tunnel junction (pMTJ) nanopillars for consumer electronics and thus operation between room temperature and ~150 °C [1]. Such devices are also of interest for cryogenic computing systems (4 K) where a persistent, fast, low-energy consuming, and nanometer scale device is needed. It is known that thermal fluctuations play an important role in spin torque switching of magnetic tunnel junctions causing magnetization fluctuations that decrease the switching voltage but also introduce switching errors. Here we explore the effect of temperature on the spin-transfer torque switching probability of state-of-the-art perpendicular magnetic tunnel junction nanopillars (40 to 60 nm in diameter) from room temperature down to 4 K, sampling up to a million switching events (see Fig. 1). We measure both the read disturb rate (as shown in Fig. 1) and the switching voltage versus pulse duration to determine the thermal stability factor Δ, the energy barrier to magnetization reversal Eb divided by the thermal energy kBT [2]. For both methods, the junction temperature at the switching voltage—obtained from the thermally assisted spin torque switching model—is found to saturate at temperatures below about 75 K (see Fig. 2). This shows that junction heating is significant below 75 K and that spin-transfer torque switching remains stochastic down to 4 K. This will be discussed along with three-dimensional finite-element simulations (COMSOL) which capture aspects of this behavior and show that this effect is associated with the reduced thermal conductivity and heat capacity of the metals in the junction. These results are important to furthering the understanding the role of temperature in spin torque switching dynamics of pMTJs and their applications as cryogenic memory. Acknowledgements This research was supported by Spin Memory Inc.

**References:**

[1] A. D. Kent and D. C. Worledge, Nature Nanotechnology 10, 187 (2015). [2] R. Heindl et al., Journal of Applied Physics 109, 073910 (2011). [3] G. D. Chaves-O'Flynn et al., Physical Review Applied 4, 024010 (2015). [4] L. Rehm et al., Appl. Phys. Lett. 115, 182404 (2019). [5] L. Rehm et al., arXiv:2009.01743.

**Images:**

![](https://assets.underline.io/uploads/markdown_image/1/image/6871e17ad509985da344e8384bada071.jpg)
Fig. 1: Switching probability (Psw) in the low-voltage (read disturb, RDR) limit as a function of voltage pulse amplitudes of a 40 nm diameter pMTJ at various bath temperatures and zero field. The pulse duration for this measurement was fixed at 10 µs. The straight lines represent fits to the data. The empty data points at 106 events stand for no errors and were therefore excluded from the fit. The dashed lines indicate the behavior expected for a device temperature of 4 K.

![](https://assets.underline.io/uploads/markdown_image/1/image/11f21c1456388cc425f73b4fee274b20.jpg)
Fig 2: Effective sample temperature Teff from the pulsed voltage ramps and RDR measurements at various temperatures between 4 and 295 K. The dotted black lines represent the expected behavior for a thermally assisted spin torque switching model based on domain wall (DW) reversal [3] with material parameters extracted from VSM and FMR measurements.

 Spin torque switching of perpendicular magnetic tunnel junction nanopillars at cryogenic temperatures

Perpendicular Double Magnetic tunnel junctions (p-DMTJ) are developed for high-performance STT-MRAM applications. In these devices, the thermal stability factor (Δ) of the storage layer (SL) magnetization is increased by sandwiching the SL between two MgO barriers thus benefiting from the interfacial perpendicular anisotropy from the two SL/MgO interfaces [1][2][3]. The critical current to switch the storage layer magnetization is reduced when using above and below the MgO/SL/MgO sandwich two antiparallel polarizers. This provides two spin-transfer torque contributions acting simultaneously on the SL. In such p-DMTJ, the two polarizers are usually pinned by exchange coupling with a synthetic antiferromagnetic structure, increasing the complexity of the stack and its patterning. Alternatively, a simplified DMTJ structure comprising a switchable assistance layer (ASL) that acts as a second polarizer was proposed [4]. It is expected to present the same enhancement in performance as traditional p-DMTJ. For these devices to work, a balance between the energy barriers of the storage layer and of the switchable assistance layer must be fulfilled. Due to the particular voltage driven dynamics, the magnetization of the switchable assistance layer should switch before that of the Storage layer. Thus, it can be set antiparallel to that of the reference layer, generating cumulative STT contributions from the ASL and reference layer. Figure.1.(a) shows a comparison of the structures of a conventional p-DMTJ versus a simplified DMTJ with ASL, as well as the layers switching sequences. Upon write, when starting from the reference (REF) up/ Storage layer down/ Assistance layer down configuration (Figure1.(b)), in order to switch the magnetization of the SL layer in the up configuration, the electrons have to flow from the REF layer to the ASL layer (positive V pulse). Since in this configuration the REF and ASL layer are in antiparallel configuration, the critical current for switching the SL magnetization is reduced. As a result the SL magnetization switches first followed by the switching of the ASL layer due to their parallel coupling and STT from the SL. When starting from the REF up/ SL up/ASL up configuration (Figure1.c), in order to switch the magnetization of the SL layer in the down configuration, the electrons have to flow from the ASL layer to the REF layer (negative V pulse). Since the ASL energy barrier is lower than the SL one, the critical current to switch the ASL magnetization in this configuration is lower than that to switch the SL magnetization. As a result, the ASL magnetization first switches antiparallel to the REF. This increases the STT efficiency on the SL magnetization, which then switches downwards ending up antiparallel to the REF. In standby conditions, the two free layers will always end up parallel, reinforcing the overall thermal stability of the device by their mutual dipolar coupling. In this work, we report the first experimental observation of the working principal of this type of devices. By comparison with a structure without the Assistance layer, the simplified double magnetic tunnel junction presents an averaged 5-fold increase of the figure of merit (D/Ic) (Figure.2). Secondly, we qualitatively interpreted the experimental observations in these devices by macrospin simulations taking into account heating effect occurring during write cycle. In fact, as a result of the presence of two MgO barriers, Joule heating plays a significant role in the write process [5]. From our model, we have been able to identify that the free layers (SL and ASL)’ blocking temperature can affect dramatically the performance of these devices. If the ASL’s blocking temperature is lower than that of the SL, the temperature rise during the application of the writing pulse can set the ASL in a paramagnetic regime. This suppresses any additional STT or dipolar coupling from this layer and causes an asymmetry on the critical voltage to switch from P to AP and from AP to P. Finally, thanks to an optimization of the structure of our simplified double magnetic tunnel junction, this issue have been solved.

**References:**

[1] B.Rodmacq et al, patent US8513944B2 (2008) [2] Daniel C. Worledge et al, IEEE MAGNETICS LETTERS, Vol 8, (2017) [3] S.Rao et al, BEOL-compatible double magnetic tunnel junction pSTT-MRAM devices for IoT and edge computing, IEDM 2020 [4] A. V. Khvalkovskiy et al, Journal of Applied Physics 124, 133902 (2018) [5] N. Strelkov et al, Physical Review B: Condensed Matter and Materials Physics, American Physical Society, 2017, 95, pp.184409 (2017)

**Images:**

![](https://assets.underline.io/uploads/markdown_image/1/image/053c6589e25028c21ebb9fef1e915cb4.jpg)
Figure 1.(a) Conventional and simplified double magnetic tunnel junctions comparison.(b) Assistance layer – Storage layer switching dynamics for P to AP states. (c) Assistance layer – Storage layer switching dynamics for AP to P states.

![](https://assets.underline.io/uploads/markdown_image/1/image/38e326aa3bd77dd523ecb03bf42ca5cd.jpg)
Figure 2.Figure of merit comparison ( Thermal stability / Critical switching current density) between Sample A with 1.5 nm of assistance layer and sample B without assistance layer as a function of Storage layer thickness.

 Modelling and Optimization of Double Magnetic Tunnel Junctions with Switchable Assistance Layer for High Performance STT-MRAM Applications

Rapid advancements in embedded memory technologies have opened the market to a wide range of low power computing applications, such as MCUs and Internet-of-Things (IoT). Innovative solutions, such as Edge computing, where data is stored and processed close to the application, have been proposed as a cost and energy-effective solution. STT-MRAM technology is an attractive candidate for edge computing memory owing to its high endurance (&gt; 1012 cycles), negligible leakage and non-volatility [1-2]. To enable adoption of eMRAM in low power applications, low active power consumption at operating frequencies ≤ 50 MHz is desirable. Reduction in the write power consumption is possible by materials engineering the free and reference layers in conventional MTJ stacks to improve switching characteristics [3, 4] and RA engineering to reduce switching voltages (Vsw) [3]. Unfortunately, Jsw improvement has often come at the cost of a lower Δ, which is unsuitable for the targeted application. An alternative approach to minimizing Jsw is to incorporate two reference layers (RLs) and MgO barriers on either side of the free layer (FL), also known as Double-MTJ (DMTJ) STT-MRAM [4] (Fig. 1a). A critical requirement is the anti-parallel alignment of the RLs which leads to a ‘doubling’ of the total spin torque. However, this approach suffers challenges in processing (two setting fields), TMR performance, RA control, stray field control, degraded retention times and back-end-of-line (BEOL) compatibility [5]. Thus, to demonstrate the feasibility of DMTJ STT-MRAM the following challenges must be addressed: Δ improvement, offset control (μoHoffset &lt; 0.1*μoHc), read/write optimization (TMR&gt;100%, Jsw &lt; 3 MA/cm2), and BEOL compatibility. In this work, we demonstrate device-level performance with full stray field compensation, best-in-class switching (Jsw) and retention (Δ) exceeding 10 years. To achieve BEOL compatibility and compensated stray fields, a 400 °C SAF-SAF design was enabled. Both the bottom-pinned and top-pinned halves of the DMTJ stack employed a synthetic antiferromagnet (SAF) design on either side of the FL. Figure 1(a, b) illustrates the stack design alongside a blanket M-H loop. The challenges involved in the design and demonstration of a 400 °C-compatible top-pinned SAF will be discussed in this work. This includes optimization of the SAF material stack design for annealing and stray field control. The successful demonstration of the SAF-SAF design is shown in the device R-H loops of CD = 80 nm devices where μ0Hoffset ~ 0 mT (Fig. 2a). Figure 2b shows the switching current density (Jsw) trends from 125 devices as a function of pulse-width. An average Jsw = 2.7 MA/cm2 at 50 ns is observed on devices with Δ = 82 kBT and TMR ~ 100%. In addition, WER curves demonstrating 1ppm error-free switching, and a wide switching-breakdown margin of ~0.7 VDC will also be presented. These performance metrics clearly exhibit the importance of the SAF-SAF design in achieving manufacturable DMTJ STT-MRAM devices, thus making it ready for implementation in low power applications.

**References:**

[1] K. Lee et. al, IEEE IEDM, pp. 2.2.1-2.2.4 (2019). [2] J. G. Alzate et. al, IEEE IEDM, pp. 2.4.1-2.4.4 (2019). [3] L. Thomas et. al., IEEE IEDM, pp 18.612-18.615 (2018) [4] G. Hu et al., IEEE IEDM, pp 19.38 – 19.41 (2019) [5] G. Hu et al., IEEE IEDM, pp. 26.3.1-26.3.4 (2015)

**Images:**

![](https://assets.underline.io/uploads/markdown_image/1/image/33428b2144a71698382f51ed049cc787.jpg)
Figure 1: (a) Schematic representation of a double magnetic tunnel junction stack with the SAF-SAF design. Two magnetic field setting steps are required to enable anti-parallel alignment in the two reference layers (RL). The stack was annealed at 400 ○C prior to patterning into devices of varying sizes. (b) Corresponding M-H loop obtained from blanket film stacks by polar MOKE measurements.

![](https://assets.underline.io/uploads/markdown_image/1/image/e612ed7842f2ae8dd9b3c918b597e014.jpg)
Figure 2: (a) Normalized TMR loops of 80 nm-sized devices comparing the optimized SAF-SAF stack design to the reference DMTJ stack, elucidating full compensation of stray fields. (b) Switching current density (Jsw) trends in a sample set of 125 devices (CD = 80 nm) measured as a function of pulse-width. Each device was switched 100 times in both directions.

 Demonstration of BEOL-compatible double magnetic tunnel junction pSTT-MRAM devices for low power computing

Spin-transfer torque magnetoresistive random access memories (STT-MRAMs) have been successfully introduced into integrated circuits owing to their non-volatility, high endurance, high-speed operation, and scalability. Since the discovery of a perpendicular easy-axis in a CoFeB/MgO material system [1], which has become the standard material system for magnetic tunnel junction (MTJ), a core building block of STT-MRAM, MTJ scaling has been accelerated while improving device performance in data retention by engineering MTJ device structure (Table 1) [2]. Here we review the MTJ scaling technology and discuss our recent results on ultra-small shape-anisotropy MTJs. Maintaining high data-retention performance, represented by thermal stability factor Δ, is essential for nonvolatile applications. Δ is proportional to total magnetic anisotropy energy density and a volume of a nanomagnet. Hence, magnetic anisotropy energy densities arising from the bulk, interface, and shape are needed to be enhanced to achieve high thermal stability as the MTJ size is scaled. Following the first demonstration of the perpendicular MTJs using a single CoFeB/MgO interface [1], those using double CoFeB/MgO interfaces were invented to enhance the interfacial anisotropy [2], resulting in high thermal stability [2] and thereby high-performance STT-MRAMs using MTJs with tens of nm in diameter for production. Once the MTJs are scaled beyond 2X nm, however, interfacial anisotropy, which is proportional to the MTJ area, becomes insufficient to achieve high thermal stability [4]. To overcome the limitation, the MTJ using quad interfaces was proposed to further enhance interfacial anisotropy for scaling down to 1X nm [5]. Still, scaling of those interfacial-anisotropy MTJs while achieving high performance is challenging for scaling beyond 10 nm. Shape anisotropy, which negatively impacts the total magnetic anisotropy in the interfacial-anisotropy MTJs, was shown to work positively in these dimensions [6]. By making a nanomagnet cylindrical with its thickness larger than its diameter, shape anisotropy turns the easy axis to the perpendicular direction instead of the in-plane easy-axis. In this way, both interfacial and shape anisotropy positively contribute to the total magnetic anisotropy, allowing one to scale MTJs beyond 10 nm. We made the MTJs with a 15-nm-thick FeB layer and achieved the MTJ scaling down to single-digit nanometers (X nm) while maintaining high Δ, yet observing STT switching [6]. Moreover, to understand the physics governing the temperature dependence of the properties of the shape-anisotropy MTJs, we studied the scaling relationship between the energy barrier E between parallel and anti-parallel states and spontaneous magnetization with respect to the temperature and compared it with that of the conventional interfacial-anisotropy MTJs. We found that E of the shape-anisotropy MTJs is less sensitive to temperature and that the shape-anisotropy MTJs have the potential to be used for wide-temperature applications at an X-nm scale [7]. The shape-anisotropy MTJ is proved to be promising for scaling down beyond 10 nm, but several challenges in the shape-anisotropy MTJ remain: (1) switching current is needed to be further reduced at short pulse and (2) an upper limit of a nanomagnetic thickness for coherent switching exists. These challenges are arising from a large volume (thickness) of a nanomagnet meeting high Δ. To address the challenges, we recently proposed the shape-anisotropy MTJ using multilayered ferromagnets, instead of a single ferromagnet [8]. The newly proposed shape-anisotropy MTJs have multilayered ferromagnets separated by MgO layer(s) so that the total ferromagnetic layer thickness can be reduced owing to the enhancement of total interfacial anisotropy. With the multilayered ferromagnet, we showed that a 5-nm-thickness reduction is achieved while obtaining the same Δ as the single ferromagnet and that the MTJs are scaled down to 2.3 nm. In addition, we demonstrated high performance in the X-nm shape-anisotropy MTJs with the multilayered ferromagnets: (1) stable switching (Fig. 1a) and high thermal stability (Fig. 1b) at high temperatures, (2) switching efficiency improvement (Fig. 1c), and (3) high-speed switching down to 10 ns with the voltage below 1 V (Fig. 1d). The shape-anisotropy MTJs in our studies use the CoFeB/MgO material system without introducing any new material. This means that the device structure can be readily employed in the existing MTJ technology by making a taller and smaller nanomagnet. Note that, not limited to the CoFeB/MgO material system, the concept of the shape-anisotropy MTJs can be adopted to other material systems; indeed, the concept was proved in Co or NiFe material systems [9]. Having the results and the versatility of the concept, the shape-anisotropy MTJs holds promise in the era of the ultimate scaling. This work was supported in part by JST-OPERA JPMJOP1611, JSAP KAKENHI JP19K04486 and JP19J12926, Cooperative Research Projects of RIEC, and DIARE of Tohoku University. J.I. acknowledges financial support from GP-Spin of Tohoku University and JST-OPERA.

**References:**

[1] S. Ikeda et al., Nat. Mater. 9, 721 (2010). [2] B. Jinnai et al., Appl. Phys. Lett. 116, 160501 (2020). [3] H. Sato et al., Appl. Phys. Lett. 101, 022414 (2012). [4] H. Sato et al., Appl. Phys. Lett. 105, 062403 (2014). [5] K. Nishioka et al., VLSI Symp., T120 (2019). [6] K. Watanabe et al., Nat. Commun. 9, 663 (2018). [7] J. Igarashi et al., Appl. Phys. Lett., to be published (2021). [8] B. Jinnai et al., IEEE IEDM, 24.6 (2020). [9] N. Perrissin et al., Nanoscale 10, 12187 (2018).

**Images:**

![](https://assets.underline.io/uploads/markdown_image/1/image/5fe6f9d12904bf2ac31236552f543ec7.jpg)
Table 1. Evolution of (Co)FeB/MgO-based MTJ structures with a perpendicular easy-axis.

![](https://assets.underline.io/uploads/markdown_image/1/image/18e8ce4784e37f1a345a22a3c60bdfce.jpg)
Figure 1. (a) R-H curves at various temperatures [left panel: CoFeB (5)/MgO/CoFeB (5) at D = 7.1 nm; right panel: CoFeB (7.5)/MgO/CoFeB (7.5) at D = 7.6 nm]. (b) Temperature dependence of Δ in the respective MTJs. (c) Switching efficiency Δ/IC0 with respect to D. (d) R-V curves at various pulse widths down to 10 ns with D = 7.6 nm.

 Material, Device Engineering, and Performance INVITED

Shape-anisotropy magnetic tunnel junction (MTJ) [1], having a cylindrical free layer, is promising for deeply scaled spin-transfer torque magnetoresistive random access memory (STT-MRAM). In shape-anisotropy MTJs, positively utilizing the shape anisotropy as well as the interfacial anisotropy allows one to reduce the MTJ diameter D below 10 nm while simultaneously keeping the thermal stability factor Δ high and capability of STT switching [1-4]. Of particular interest in the shape-anisotropy MTJs is the magnetization reversal mode, which is critical in quantifying Δ with high accuracy. In the conventional interfacial-anisotropy MTJs with such a small size (D &lt; 30 nm), magnetization dynamics of the free layer can be reasonably described by a single-domain (coherent reversal) model. On the other hand, in shape-anisotropy MTJs, micromagnetic simulation in previous studies suggests that magnetization reversal mode depends not only on D but also on the thickness t; the MTJs with too-thick a free layer (t &gt; ~30 nm) switch incoherently, imposing an upper limit of Δ and also causing a switching delay [2,5]. In this study, we experimentally study the magnetization reversal mode in shape-anisotropy MTJs with various free layer thicknesses and diameters to reveal the crossover of coherent/incoherent reversal. A stack structure of, from the substrate side, Ta (5)/Ru (10)/Ta (15)/synthetic ferrimagnetic reference layer/MgO/(Co0.25Fe0.75)75B25 (t = 15, 30, and 50)/MgO/Ru (5) is deposited by dc/rf magnetron sputtering on a thermally oxidized Si substrate. The numbers in parentheses are nominal thicknesses in nm and t represents the free-layer CoFeB layer thickness. For some samples with t = 50 nm, Ta (5) capping layer is used instead of MgO, which is confirmed to have little impact on the findings described below. The stacks are processed into circular MTJs with various D by electron beam lithography, reactive ion etching, and multistep Ar ion milling [1]. To study the magnetization reversal mode, we evaluate astroid curves by measuring the magnetic-field-angle dependence of switching fields [6,7]. We also investigate the thickness range in which the coherent reversal model is applicable by comparing Δ values experimentally determined under an assumption of the coherent reversal and those expected from the calculation. Figure 1 shows the magnetic-field-angle dependence of a switching field in a cartesian coordinate, the so-called astroid curve, for the shape-anisotropy MTJs with t of 15 nm and 50 nm. The solid curve is the best fit based on the coherent reversal model as used in [6]. As can be seen, the fitting degree is different for each t. For t = 15 nm, the experimental result is well explained by the fit, indicating a coherent reversal, which is consistent with the previous result on a FeB-based shape-anisotropy MTJ with the same free-layer thickness [5]. On the other hand, for the t = 50 nm case, the fit is poor; the switching field along the easy-axis (μ0Hx = 0 mT, where μ0 is the permeability in vacuum) is smaller compared with the other angles (|μ0Hx| &gt; 0). Such a distortion is also seen for t = 30 nm with D &gt; ~15 nm. Similar behavior was reported in a Py nanowire, and was explained by a buckling mode [9]. The similarity suggests that magnetic moments in the shape-anisotropy MTJs with a thicker and larger-diameter free layer is reversed incoherently via an oscillatory buckling along the thickness direction. Next, we measure the switching probability using a pulsed magnetic field and evaluate Δ with a coherent reversal model [10]. The obtained Δ is plotted as a function of D in Fig. 2. The solid curves represent the calculation based on the coherent reversal model, where the whole volume contributes to the energy barrier. For D &lt; ~15 nm, the measured Δ value agrees well with the calculated one, whereas D &gt; ~15 nm is much smaller, backing up interpretation of the difference observed in the astroid-curve measurement as crossover of the magnetization reversal mode. In summary, we investigate the magnetization reversal mode and thermal stability factor in shape-anisotropy MTJs with various free-layer thicknesses and diameters. We reveal that the magnetization reversal in the MTJs with thicker and larger-diameter free layer proceeds incoherently, affecting the retention property. This study provides a key understanding of the magnetization reversal in the shape-anisotropy MTJs. This work was supported in part by JST-OPERA, JSPS KAKENHI (JP19J12926 and JP19K04486), and DIARE. J.I. and K.W. acknowledge financial support from GP-Spin and JST-OPERA.

**References:**

[1] K. Watanabe et al., Nature Commun. 9, 663 (2018). [2] N. Perrissin et al., Nanoscale 10 12187 (2018). [3] J. Igarashi et al., Appl. Phys. Lett., to be published (2021). [4] B. Jinnai et al., IEEE IEDM, 24.6.1 (2020). [5] K. Watanabe et al., International Conference on Magnetism 2018, F6-01 (2018). [6] N. Kikuchi et al., IEEE Trans. Magn. 41, 3613 (2005). [7] R. Dittrich et al., J. Appl. Phys. 97, 10J705 (2005). [8] J. Igarashi et al., Appl. Phys. Lett. 111, 132407 (2017). [9] A. B. Oliveria et al., Phys. Rev. B 78, 024423 (2008). [10] Z. Li et al., Phys. Rev. B 69, 134416 (2004).

**Images:**

![](https://assets.underline.io/uploads/markdown_image/1/image/09cef5af19c31a24332dd558ca93eedc.jpg)
Figure 1 Experimental results of magnetic-field-angle dependence of switching field in the shape-anisotropy MTJs for the thickness of (a) 15 nm and (b) 50 nm with MgO capping layer. The lines correspond to the best fitting based on the coherent reversal model.

![](https://assets.underline.io/uploads/markdown_image/1/image/7af8e6f3b37af4ec0b1579568cbc20eb.jpg)
Figure 2. Thermal stability factor Δ as a function of D in the shape-anisotropy MTJs for the thickness of 15 [4], 30, and 50 nm. For the samples with t = 50 nm, Ta (5) capping layer is used. The curves correspond to the calculation based on the coherent reversal model.

 Crossover of magnetization reversal mode with thickness and diameter in shape-anisotropy magnetic tunnel junctions

The perpendicular Spin-Transfer-Torque Magnetic Random Access Memory (p-STT-MRAM) is one of the most promising emerging non-volatile memory technologies. As these devices are limited by their thermal stability factor at technological nodes smaller than 20 nm, their downsize capability is compromised. Indeed, as the device shrinks, there is a decrease in thermal stability due to a decrease in the total interfacial perpendicular anisotropy energy proportionally to the cell area. This decrease significantly reduces the retention time of the memory [1-3]. A promising solution to this problem relies on taking advantage of the shape anisotropy of the storage layer by increasing its thickness to values larger than its diameter. The shape anisotropy becomes out-of-plane, with strength proportional to the large volume of the thick cell, bringing an additional robust and tunable source of perpendicular anisotropy on top of the interfacial perpendicular anisotropy. These two sources of anisotropy allow to extend the downsize scalability of STT-MRAM towards sub-20 nm technological nodes [4, 5]. However, the storage layer thickness also affects the writing operation of the cell and should be examined. In this work, the magnetization reversal mechanism of the PSA-STT-MRAM induced by STT was numerically studied. Micromagnetic simulations were carried out (with and without the effect of thermal fluctuations), enabling the identification of different modes of magnetization reversal in this memory. An initial study comprises pillars with aspect-ratios (AR) between 0.8 and 3, with a fixed diameter of 20 nm. It was shown that, for an AR smaller than 1, the mechanism of reversal follows a macrospin-like reversal. When increasing the AR, a non-coherent reversal develops, which evolves from a buckling-like reversal to a transverse-domain wall nucleation-propagation at higher aspect ratios. This latter mode of reversal is associated with the slowing down of the switching dynamics, an effect which worsens as the layer thickness is increased [Fig. 1]. The inverse of the switching time follows a linear relationship with the applied voltage, a law conserved when considering thermal fluctuations. This demonstrates that, even though the nucleation process is assisted by thermal fluctuations, the reversal is controlled by the STT. Changing both the diameter and the thickness but maintaining a thermal stability factor of around 80 it is observed that the minimum voltage to reverse the storage layer increases [Fig. 2]. We interpret as the weakening influence of the strong interfacial STT of tunnelling electrons. This comes along with a transition from a macrospin-like reversal to a buckling-like reversal when AR is increased, despite the thermal stability value is in the same range. This study shows the possibility to obtain a macrospin-like reversal at low applied voltages at sub-20 nm magnetic tunnel junctions. With their switching time of the order of tens of ns, these PSA-STT-MRAM are not fast-enough memories suitable for Cache application but should be functional for dense DRAM type of applications. Also, the junction Resistance x Area product must be lowered compared to conventional STT-MRAM to maintain the write voltage significantly below the barrier breakdown voltage.

**References:**

[1] C. Yoshida et al, Jpn. J. Appl. Phys. 58, SBBB05 (2019). [2] H. Sato et al, Jpn. J. Appl. Phys. 58, 0802A6 (2017). [3] L. Thomas et al, J. Appl. Phys. 115, 172615 (2014). [4] N. Perrissin et al, Nanoscale 10, 12187-12195 (2018) [5] K. Watanabe et al, Nat. Com. 9, 663 (2018).

**Images:**

![](https://assets.underline.io/uploads/markdown_image/1/image/f528241113b078615ca57fd5629207ff.jpg)
Fig 1: Time traces of the mean reduced magnetization 〈mz〉for different pillar thicknesses for an applied voltage of -3 V.

![](https://assets.underline.io/uploads/markdown_image/1/image/67e3ba17811e7244cfa1ee6d319e6030.jpg)
Fig 2: Voltage dependence of the time to reverse 50% of the magnetic layer (switching time - τswitch) for different pillar sizes.

 Magnetization reversal driven by spin-transfer-torque in sub-20 nm perpendicular shape anisotropy magnetic tunnel junctions

Voltage-controlled magnetization switching is of great interest for high density, low energy, fast, and non-volatile memory applications. We propose a new type of two-terminal voltage-controlled magnetic tunnel junction (MTJ) that uses a resonant tunnel barrier (see figure), unlike a conventional MTJ that uses a thin oxide tunnel barrier. The resonant tunnel barrier consists of two oxide layers sandwiching a non-magnetic spacer layer known to exhibit a large interlayer exchange coupling, e.g., Ru, Rh, Ir, etc. A voltage across the structure can control the transmission coefficient between the fixed and the free magnets via the discrete energy states within the resonant tunnel barrier. A resonance-enhanced transmission coefficient leads to an interlayer exchange coupling between the two magnets, the strength of which is determined by the properties of the non-magnetic spacer material. The resonance-enhanced coupling (REC) energy exhibits a voltage-dependent oscillation in sign and the peak equivalent exchange field is strong enough to switch typical ferromagnets used in scaled magnetic memory devices. The free magnet switches to become either antiparallel or parallel to the fixed magnet, if the coupling energy sign is positive or negative, respectively. After the switching, the configuration is retained as the equilibrium interlayer exchange coupling is negligible, suppressed by the large barriers. This mechanism allows us to achieve a bidirectional switching with the same voltage polarity, unlike conventional magnetic devices, where a bidirectional current or a magnetic field is necessary. The threshold exchange coupling energy for switching is determined by only the equivalent anisotropy energy of the free magnet. Based on non-equilibrium Green's function-based calculations, we show that the device current can be significantly low at switching, in the order of ≤104 A/cm2, in a structure made with existing materials, e.g., CoFeB/MgO/Ru/MgO/CoFeB. The proposed device can provide a few fJ switching energy and ≤1ns switching speed. The switching threshold is decoupled from the speed due to the conservative nature of the exerted torque, unlike the conventional spin-torque devices that exhibit a trade-off due to the nonconservative nature of the switching torque. This feature is very attractive to achieve a magnetoresistive random access memory (MRAM) technology, REC-MRAM, with a significantly low energy-delay product. The magnetization state of the free magnet can be read out with magnetoresistance of the two-terminal device, which is ~30% for the materials combination under consideration. In this new mechanism, the magnetoresistance is higher for smaller voltages, while the exchange field is higher for larger voltages—this is promising for efficient read and write operations in potential memory applications. This work is in part supported by ASCENT, one of six centers in JUMP, a SRC program sponsored by DARPA and in part by the Center for Energy Efficient Electronics Science (E3S), NSF Award 0939514.

**References:**

[1] S. Sayed et al., Phys. Rev. Applied 14, 034070, 2020.

**Images:**

![](https://assets.underline.io/uploads/markdown_image/1/image/d88a4e578946f8bbcbe1621b22b34bfc.jpg)
A new kind of magnetic tunnel junction with a resonant tunnel barrier. A voltage across the structure can tune the transmission coefficient, which in turn induces a large oscillatory interlayer exchange coupling that can switch the free layer in both directions depending on the coupling energy sign.

 Resonance-enhanced exchange coupling for voltage-controlled magnetization switching

The rising demand for high efficiency computing has driven development pursuits to identify a “beyond-CMOS” dimensionally scalable logic technology. Superconducting technologies (such as reciprocal quantum logic) offer a solution to this growing challenge; however, these systems require a compatible low temperature memory solution that is power efficient, dense, and fast. To meet this need, Josephson magnetic random access memory (JMRAM) is being pursued. [1-4] In its simplest form, JMRAM combines superconducting electrodes (S) with a ferromagnetic (F) spin valve to form magnetic barrier Josephson Junctions (MJJs). JMRAM optimization requires that magnetic layers exhibit single domain switching with abrupt magnetization reversal and low switching fields, at cryogenic temperatures. JMRAM requirements are further complicated as materials selection and thicknesses must allow MJJs to carry a sufficient critical current (Ic), consistent with low error rate operation, at 4K. In this work, we show fundamental low temperature (T) magnetic and Ic responses of a model S/F/S system – Nb/CoFeB/Nb – and relate this to roughness effects that arise in ultra-thin film systems. Ultra-thin CoFeB films (6-13 Å) deposited onto 1500 Å Nb/50 Å Cu and 1500 Å Nb/ML (ML = (10 Å Cu/5 Å Nb)6/10 Å Cu) and capped with 50 Å Cu/500 Å Nb have been examined structurally, magnetically and electrically. Prior work has shown improved magnetic switching and decreased surface roughness with the incorporation of the ML structure as a buffer under the ferromagnetic layer. [4] The film thicknesses and amorphous structure were confirmed with x-ray reflectivity and diffraction. The magnetic character was probed at 300 K and compared to the 10 K response. MJJ Ic was measured at 4 K. Here, CoFeB films exhibit low reversal fields at 300 K (Fig 1a), analogous to MRAM devices that utilize CoFeB as a soft ferromagnet with a MS value ~ 1525kA/m. Patterned films, measured at 10 K, show an expansion of the magnetic hysteresis (Fig 1b). Incorporation of the ML buffer shows reduced coercivity (Fig. 1a, T = 300 K) and improved squareness (Fig. 1b, T = 10 K). In electrical devices, the Ic through the CoFeB layer decays exponentially with increasing CoFeB thickness and shows a dip in Ic at 8 Å (Fig 2), characteristic of a change in the equilibrium Josephson phase in an S/F/S structure, the “0 – π” thickness. While the ultimate objective of these efforts is to achieve a cryogenic memory solution, the work described here probes the fundamental properties of low T magnetics and S/F/S character of a candidate material for this emerging technology.

**References:**

[1] IM Dayton, MG Loving et al. “Experimental Demonstration of a Josephson Magnetic Memory Cell With a Programmable pi-Junction” IEEE Magnetics Letters 9, 1 (2018) [2] A. Herr and Q. Herr "Josephson Magnetic Random Access Memory System and Method". US Patent US20110267878 A1, 30 April 2010 . [3] MG Loving, TF Ambrose, Ferrimagnetic/ferromagnetic exchange bilayers for use as a fixed magnetic layer in a superconducting-based memory device, US Patent App. 16/256,547, 2020 [4] TF Ambrose, MG Loving, Repeating alternating multilayer buffer layer, US Patent No: 10879447 B2, 29 December 2020

**Images:**

![](https://assets.underline.io/uploads/markdown_image/1/image/59d7948c169f880570f521dd13750027.jpg)
Fig 1: Comparison of a) room temperature (T = 300 K) blanket film measurements and b) low temperature (T = 10 K) patterned array magnetic switching. Both data sets show improved magnetic performance with the ML buffer.

![](https://assets.underline.io/uploads/markdown_image/1/image/a357a3de541197ac98981bfa3a030c17.jpg)
Fig. 2: Comparison of the buffer layer impact on Ic vs. CoFeB thickness, in Angstroms

 Magnetic Reversal and Critical Current Transparency of CoFeB Superconductor-Ferromagnet-Superconductor Heterostructures

The current information technology has been relied on von Neumann type computation [1]. In order to manage the recent digital universe and big data, it is essential to investigate alternative technologies to sustain the development in computation. Among them, neuromorphic computation has been attracting intensive studies using the current complementary metal oxide semiconductor (CMOS) architecture and beyond in the last decade to mimic the functionality and operation of a synapse in a brain. A promising synapses operation has been demonstrated via the stochastic operation of a magnetic tunnel junction (MTJ) [2]. However another important feature of a synapse, memory potentiation, has been overlooked to date. In this study we have demonstrated memory functionality via current-induced annealing in a giant magnetoresistive (GMR) junction with ferromagnetic Heusler alloy films. A GMR junction consisting of Cr (3)/W (10)/Co2FeAl0.5Si0.5 (CFAS) (10)/Ag (3)/CFAS (2.5)/Ru (3) (thickness in nm) was fabricated as an artificial synapse with achieving a low resistance-area product for low power consumption. Here we recently reported the reduction in the crystallisation temperature by promoting layer-by-layer growth on a (110) surface [3], of which is comparable with Joule heating induced by a controlled current introduction. The multilayered stack was grown on a thermally oxidised Si substrate using a high target utilisation sputtering system (PlasmaQuest, HiTUS) at room temperature. The stack was patterned into a nanopillar junction using a combination of electron-beam lithography and Ar-ion milling. The seed layer, Cr/W, was patterned into a bottom electrode with a width of 100-200 nm. Just above the bottom Heusler-alloy layer was patterned into a nanopillar with a diameter between 80 and 200 nm, followed by the patterning of a top electrode with Ti/Au. The fabricated nanopillars were measured using a probe station (HiSOL, HMP-400 SMS) with a conventional four-terminal method with a constant current source (Keithley, 2400) and a nanovoltmeter (Keithley, 2182a). The resistance changes were measured after a series of current pulse applications of 500 µA up to 5 mA for 100 µs up to 500 µs. Little change was observed at 500 μA, which was used for GMR measurements, while monotonic resistance change was measured above 1 mA with the repetition of 100 µs pulse introduction, confirming the current-induced crystallisation of CFAS(110) and the associated change in the resistivity. The Heusler-alloy crystallisation was then observed using transmission electron microscope (TEM; JEOL, JEM-2200FS) by thinning with focused ion beam (FIB, FEI, Nova 200 Dual Beam). The crystallinity of the CoFeAl0.5Si0.5 has been confirmed using nanobeam, which shows some CFAS(220) diffraction spots within polycrystalline ring feature. TEM imaging confirmed CFAS was partially crystallised with maintaining a smooth interface of &lt; 1 nm roughness in the GMR junction. Due to the nature of a simple electrical current introduction employed in this study, the GMR junction does not require post-annealing processes but it can stores the operation cycle permanently as the change in the resistivity. Hence such current-induced crystallisation can be used in a neuromorphic node network, which can revolutionalise solid state memory.

**References:**

[1] B. V. Benjamin, P. Gao, E. McQuinn, S. Choudhary, A. R. Chandrasekaran, J.-M. Bussat, R. Alvarez-Icaza, J. V. Arthur, P. A. Merolla and K. Boahen, K. Neurogrid Proc. IEEE, vol. 102, p. 699 (2014). [2] J. Grollier, D. Querlioz, and M. D. Stiles, Proc. IEEE, vol. 104, p. 2024 (2016). [3] J. Sagar, L. R. Fleet, M. Walsh, L. Lari, E. D. Boyes, O. Whear, T. Huminiuc, A. Vick and A. Hirohata, Appl. Phys. Lett., vol. 105, p. 032401 (2014).

**Images:**

![](https://assets.underline.io/uploads/markdown_image/1/image/e0321b566666d32b22e641e5de173bf6.jpg)
Fig. 1 Evolution of magnetic moment and grain size of the Heusler alloy films and their corresponding crystalline structures.

 Current-Induced Crystallisation in Heusler Alloy Films

As the crucial device element for next-generation cache and edge computing technologies, the magnetic tunnel junction (MTJ) has been widely studied with recent focus towards using spin-orbit torque (SOT) to switch the free layer magnetization. Writing the MTJ using SOT approach is attractive, because it can increase the junction endurance as switching current path does not go through the tunneling barrier. In this work, we aim to enhance the SOT switching efficiency in the MTJ through various interlayer insertion designs in the free layer. Our study is carried out using in-plane MTJ (IP-MTJ), which has been demonstrated that no external magnetic field is required for SOT switching [1]. We fabricated W underlayer-based IP-MTJs, and investigate how the insertion layer between the W and CoFeB free layer affects the switching current density of the MTJ. Interestingly, with the insertion of ultra-thin layers such as MgO, Ru and TiW, the switching current drops significantly with the MgO insertion offering ~70% of reduction. Here, standalone 3-terminal IP-MTJ devices of elliptical sizes 300 nm x 600 nm are fabricated using Canon X5 stepper lithography on 8 inch Si wafers. We measure the pulse current switching loops with our home-built probe station [2]. Without insertion layer, the switching current is ~11.9 mA, equivalent to ~1.9x1011 A/cm2. The large value of switching current density is because of the dramatic reduction in the spin Hall angle (SHA) of W underlayer after annealing at 330°C, which also leads to a structural phase change to α-W. While the introduction of an insertion layer universally reduces the current density. The MgO interlayer reduces it by more than 3 times making it superrior for insertion layer selection. To understand it better, we performed spin-torque ferromagnetic resonance (ST-FMR) measurement [3] to determine the damping constant, spin Hall angle, and effective saturation magnetization (Ms_eff). A representative example of ST-FMR spectra for MgO insertion layer is shown in Fig. 1. We found the thin insertion layer has little influence on the damping constant, but some modifications in Ms_eff and SHA are found, which can be correlated with the switching current reduction results. Further investigations on the role of insertion layer thickness are ongoing and are expected to reveal the optimal insertion layer for SOT current reduction.

**References:**

[1] L. Liu, C.F. Pai, Y. Li et al., Science, Vol. 336, p.555 (2012) [2] J. Lourembam, J. Huang, S.T. Lim et al., AIP Adv., Vol. 8, p.055915 (2017) [3] L.S. Huang, S.K. He, Q.J. Yap et al., Appl. Phys. Lett., Vol. 113, p.022404 (2018)

**Images:**

![](https://assets.underline.io/uploads/markdown_image/1/image/ad011acedbe5cfe942648e452a3ab9a6.jpg)
Fig. 1 Field sweep ST-FMR spectra of W/MgO/CoFeB/MgO film. The RF frequency varies from 7 to 20 GHz.

Advanced MTJ and SOT Technology for AI and Automobile applications INVITED

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